In the article, Blocking And Non-blocking in Verilog, we will discuss the topics of Verilog blocking and non-blocking.

1. Systemverilog Spec
2. Define In Systemverilog
3. Verilog Vs Systemverilog
4. Systemc Vs Systemverilog

Blocking And Non-blocking In Verilog:

The execution of the blocking statements will be in series. This blocking statement will block the next statement until the present statement executes successfully.

Defines the size of the memory block. Note the use of the Verilog as there is in VHDL. Just like the shift register model from November, the parameterisable bidirectional port.

1. Verilog - Modules The module is the basic unit of hierarchy in Verilog I Modules describe: I boundaries module, endmodule I inputs and outputs ports I how it works behavioral or RTL code I Can be a single element or collection of lower level modules I Module can describe a hierarchical design (a module of modules).
2. Interfaces are a major new construct in SystemVerilog, created specifically to encapsulate the communication between blocks, allowing a smooth refinement from abstract system-level through successive steps down to lower RTL and structural levels of.

The execution of the non-blocking statements will be in parallel. This non-blocking statement first it will evaluate all RHS values after that all this will be assigned to the LHS at a time.

Systemverilog Spec

The Eda playground example for the Blocking:

The Eda playground example for the Non-blocking:

The following process will explain how blocking and non-blocking procedural statements will execute:

Define In Systemverilog

1. At the current time-slot, the simulator will evaluate the right-hand side of all assignment statements, those are related to Non-blocking statements.
2. All the blocking procedural statements will execute at the same time, all the non-blocking statements are set aside for processing.
3. The non-blocking procedural statements with no timing controls will execute in this third stage.
4. The non-blocking procedural statements with timing controls will execute in this 4th stage.
5. Advance the simulation clock.

Finally, we completed the article blocking and non-blocking in Verilog with the topics of Verilog blocking and non-blocking. In the next post, we will discuss the event Scheduling in Verilog.

(30)Without using randomize method or rand,generate an array of unique values?
Ans:-
(32)What is the difference between byte and bit [7:0]?
Ans:-
byte is signed whereas bit [7:0] is unsigned.
(33)What is the difference between program block and module?
Ans:-
Program block is newly added in SystemVerilog. It serves these purposes

1. It separates testbench from DUT
2. It helps in ensuring that testbench doesn't have any race condition with DUT
3. It provides an entry point for execution of testbench
4. It provides syntactic context (via program ... endprogram) that specifies scheduling in the Reactive Region.

1. Program blocks can't have always block inside them, modules can have.
2. Program blocks can't contain UDP, modules, or other instance of program block inside them. Modules don't have any such restrictions.
3. Inside a program block, program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. No such restrictions on module
   
4. Program blocks get executed in the re-active region of scheduling queue, module blocks get executed in the active region
5. A program can call a task or function in modules or other programs. But a module can not call a task or function in a program.

1. http://www.project-veripage.com/program_blocks_1.php and few more next/next !!!
2. Section 16, SystemVerilog LRM 3.1a ... It's worth the effort reading line-by-line (and between the lines if you can :) ).
   

Verilog Vs Systemverilog

Systemc Vs Systemverilog